Non-volatile memory is a class of data storage in which data stored thereon is retained in the absence of power. Examples include magnetic hard disk drives (HDD) commonly used in computer workstations by example, and non-volatile memory chips commonly used in mobile devices and portable electronic devices such as music players and smart phones by example. A common type of non-volatile memory chip is the flash memory chip. Flash memory chips can be used in any application where data needs to be retained in the absence of power.
Example applications of flash memory chips include NVRAM (non-volatile random access memory), USB (Universal Serial Bus) flash drives and solid state disk drives (SSD), which use one or more flash memory chips to store large amounts of data even when disconnected from a power supply. Another application of flash memory chips is NVDIMM (non-volatile dual in line memory module), which combines both volatile memory such as DRAM (dynamic random access memory) and flash memory on a printed circuit board (PCB). NVDIMM can also be used for RAID (Redundant Array of Independent Disks) adapter cards to cache data in the event of a power outage; they can be used for taking “memory snapshots” where the entire memory contents are captured and stored in the flash memory at pre-determined intervals for mission critical applications; and they can provide an additional layer of tiered memory support with persistence, to store metadata, for databases and on line transaction processing. Other example applications of NVRAM and NVDIMM are not listed here.
One of the well-known problems of flash memory, which extends to NVRAM and NVDIMM which use flash memory, is the time required to program data to the flash memory. For example, the time to write the same amount of data to flash memory can be several times slower than it would take to write to DRAM. By example, the time required to write data to one type of flash memory referred to as single level per cell (SLC) can range between 500 μs to 600 μs, while another type of flash memory referred to as multiple level per cell (MLC) can have longer write times ranging between 1 ms to 1.5 ms. While this may not be an issue in applications where time is not critical, there may be high performance (high speed) applications that demand faster programming times. One example application is using NVDIMM to cache or backup all data of the DRAM in the event of a power failure affecting the host system in which the NVDIMM is connected to and powered from.
FIG. 1A is a block diagram illustrating a generic NVDIMM of the prior art. The NVDIMM of FIG. 1A includes DRAM memory 10, flash memory 12, an NVDIMM controller 14, a switch circuit 16 connected to a PCB (not shown) having conductor traces formed thereon for interconnecting the devices. The memory chips of the DRAM memory 10 and the flash memory 12, as well as the chips of the NVDIMM controller 14 and of the switch circuit 16, are encapsulated in plastic packages. A single flash package can include multiple flash dies connected in parallel with each other. An edge connector physical interface 18 of the PCB is connectable to a slot of the motherboard of the host system. Other devices may be present on the PCB of the NVDIMM, but are not shown in FIG. 1A. It is noted that FIG. 1A shows a single DRAM memory 10 package and a single flash memory 12 package, each representing a collective group of DRAM flash memory packages, as the number of memory device packages depends on the capacity of each memory package and the desired total memory capacity of the NVDIMM.
In normal operation, DRAM memory 10, flash memory 12, NVDIMM controller 14, switch circuit 16, and any other devices, are provided with a regulated voltage MOBO_VR provided from the motherboard. This power can be provided via the edge connector 18 and routed by the PCB conductor traces. In normal operation as shown in FIG. 1A, the DRAM receives write data from the edge connector 18 via switch 16, and provides read data to the edge connector 18 via switch 16. Periodically, the NVDIMM controller 14 checks the status of flash memory 12 to ensure it is working.
FIG. 1B illustrates the interaction of the devices of FIG. 1A in the event of an unexpected power failure. When the host system experiences a sudden loss of power, a backup mode of operation is entered where a backup power supply BACKUP_PWR is immediately activated to provide temporary power to all the devices on the PCB, and a “save” control signal is issued to the NVDIMM controller 14. In response to the “save” control signal, the NVDIMM controller 14 controls switch 16 to decouple the DRAM memory 10 from the edge connector 18, and to couple the DRAM memory 10 to the NVDIMM controller 14, which then issues operations to write all the DRAM data to the flash memory 12.
The problem with this backup operation is that all the data of the DRAM memory 10 must be copied, or written, to the flash memory 12 within a short time span, such as between 25 to 30 seconds for example. It should be noted that this backup time involves at least two components. First is a data transfer time of data from the DRAM memory 10 to the flash memory 12, and second is the internal flash memory programming time which is executed when the flash memory has received the data it is to program. The following example highlights the problem with current NVDIMM's.
If the NVDIMM includes 4 GB of DRAM, then all 4 GB must be copied into Flash memory. Currently the smallest capacity flash memory chip is 4 GB in size and the largest commonly available page size is 16 kB for the 4 GB memory chip, where up to one page of data can be written in one program cycle of the flash memory chip. The page of a flash memory chip is inherent to the device architecture and cannot be increased. It is first noted that the flash memory can be configured to store 2 bits per cell (MLC) or a single bit per cell (SLC). Some MLC flash memory can be configured to operate in an SLC mode. Example worst case MLC program times for one page of data is between 1.3 ms to 1.5 ms. An MLC flash memory chip operating in SLC mode can have worst case program times of about 600 μs. In contrast, worst case SLC program times for one page of data is about 350 μs.
The ideal backup configuration would be to use a single 4 GB flash memory chip to store 4 GB of DRAM data, as this would minimize the number of flash memory chips that is required. However, even the SLC programming times are too slow to achieve programming of all 4 GB within a 30 s time window. Therefore, multiple 4 GB flash memory chips are programmed in parallel to increase the number of pages which can be programmed at substantially the same time. Table 1 below presents different configurations of 4 GB flash memory chips (dies) each having a 16 kB page size, and the corresponding backup time required to backup all 4 GB of DRAM data. These times include the data transfer time from the NVDIMM controller to the flash memories and the internal flash memory programming time.
TABLE 1Configuration (Flash type/# of 4 GB die)Backup time (s)MLC/2-die180-200MLC/3-die120-140MLC/4-die100MLC(SLC mode)/3-die60-70SLC/2-die 60
While MLC flash chips are more cost effective than SLC flash chips of the same storage density, as can be seen from Table 1, even the case of 4 MLC chips operating in parallel would not operate fast enough to program 4 GB of DRAM data within 30 s. It can be seen that additional 4 GB chips operating in parallel are needed in order to attain the desired backup time. However, now the problem of overprovisioning of flash memory is introduced, where the total capacity of the flash memory exceeds that of the DRAM by a significant factor. This undesirably increases cost of the NVDIMM as more flash chips are needed.
It is, therefore, desirable to provide a memory system having non-volatile memory backup with higher speed programming capability at minimal cost.